1. Field of the Invention
The present invention is directed in general to the field of semiconductor fabrication and integrated circuits. In one aspect, the present invention relates to forming PMOS field effect transistors (FETs) as part of a complementary metal oxide semiconductor (CMOS) fabrication process.
2. Description of the Related Art
CMOS devices, such as NMOS or PMOS transistors, have conventionally been fabricated on semiconductor wafers with a surface crystallographic orientation of (100), and its equivalent orientations, e.g., (010), (001), (00-1), where the transistor devices are typically fabricated with a <100> crystal channel orientation (i.e., on 45 degree rotated wafer or substrate). The channel defines the dominant direction of electric current flow through the device, and the mobility of the carriers generating the current determines the performance of the devices. While it is possible to improve carrier mobility by intentionally stressing the channels of NMOS and/or PMOS transistors, it is difficult to simultaneously improve the carrier mobility for both types of devices formed on a uniformly-strained substrate because PMOS carrier mobility and NMOS carrier mobility are optimized under different types of stress. For example, some CMOS device fabrication processes have attempted to enhance electron and hole mobilities by using strained (e.g. with a bi-axial tensile strain) silicon for the channel region that is formed by depositing a layer of silicon on a template layer (e.g., silicon germanium) which is relaxed prior to depositing the silicon layer, thereby inducing tensile stress in the deposited layer of silicon. Such processes enhance the electron mobility for NMOS devices by creating tensile stress in NMOS transistor channels, but PMOS devices are insensitive to any uniaxial stress in the channel direction for devices fabricated along the <100> direction. On the other hand, attempts have been made to selectively improve hole mobility in PMOS devices, such as by forming PMOS channel regions with a compressively stressed SiGe layer over a silicon substrate. However, such compressive SiGe channel PMOS devices exhibit a higher sub-threshold slope (SS) and higher voltage threshold temperature sensitivity. This is in large part due to a degraded quality of the interface between the compressive SiGe layer and the dielectric layer which is quantified by the channel defectivity or interface trap density (Dit) in the PMOS devices.
Accordingly, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.